States defining the CONTROL bus:

Important definitions:
----------------------
!ZERO  =  A2| A3|A4|A5|A6|A7|A8|A9|A10|A11|A12|A13|A14|A15
!FOUR  = !A2| A3|A4|A5|A6|A7|A8|A9|A10|A11|A12|A13|A14|A15
!EIGHT =  A2|!A3|A4|A5|A6|A7|A8|A9|A10|A11|A12|A13|A14|A15
!CEE   = !A2|!A3|A4|A5|A6|A7|A8|A9|A10|A11|A12|A13|A14|A15
--------------------------------------------------------------------------------
CONTROL(0): Enable for FTOW drivers.
	FTOW_EN

CONTROL(1): Enable for Tracking receivers.
	TRACK_SRC

CONTROL(2)*: OC* for the TrackIn Register.
	LOAD & (BLOCK6|BLOCK7|BLOCKF)

CONTROL(3): CLK for the TrackIn Register.

CONTROL(4)*: CE* and OE* for the tracking MLUs on towers 0-5
	!(LOAD & (BLOCK6&!BLOCK3&!BLOCK4))

CONTROL(5)*: CE* and OE* for the tracking MLUs on towers 6-11
	!(LOAD & (BLOCK7&!BLOCK4&!BLOCK5))

CONTROL(6): CLK for the Diag Register in the Tracking block.
	BLOCK9 & ZERO & !DS* & WRITE

CONTROL(7)*: OC* for the Diag Register in the Tracking block.
	TRACK_SRC

CONTROL(8)*: Enable for address bus buffers to tracking MLUs.
	!(LOAD & (BLOCK6|BLOCK7|BLOCKF) & !(A10|A11|A12|A13|A14|A15))

CONTROL(9)*: Enable for data buffer to read out the TrackIn Register.
        !(LOAD & (BLOCKF&!(A10|A11|A12|A13|A14|A15))) &
	!(BLOCK9 & ZERO & !WRITE)
	
CONTROL(10)*: OE* for the buffers for VME_DATA to Tracking MLUs(0-5).
	!((LOAD|!WRITE) & (BLOCK6&!BLOCK3&!BLOCK4) & !(A10|A11|A12|A13|A14|A15))

CONTROL(11)*: OE* for the buffers for VME_DATA to Tracking MLUs(6-11).
	!((LOAD|!WRITE) & (BLOCK7&!BLOCK4&!BLOCK5) & !(A10|A11|A12|A13|A14|A15))

CONTROL(12)*: WE* for all the tracking MLUs.
        !(LOAD & WRITE)

CONTROL(13)*: DIR* of various tranceivers on board.
	WRITE

CONTROL(14)*: OE* of the Tower Register.
	!TOWIN_SRC | (LOAD & (BLOCK0|BLOCK1|BLOCK2) & !(A12|A13|A14|A15))

CONTROL(15): CLK for the Tower Registers.

**NOTE: If you are in run mode the address doesn't matter because you
	are no allowed to write to the data path in VME.  All you read 
	back is what is on the outputs of the OG and TT MLUs.  Probably 
	a useless function but easy enough to implement.

CONTROL(16)*: CE* and OE* for offset and gain MLUs(0-3).
	(LOAD & !((LOAD & (BLOCK0&!(A12|A13|A14|A15))) |
	(!WRITE & BLOCK0))) | (LOAD & BLOCKA & ZERO)

CONTROL(17)*: CE* and OE* for offset and gain MLUs(4-7).
	(LOAD & !((LOAD & (BLOCK1&!(A12|A13|A14|A15))) |
	(!WRITE & BLOCK1))) | (LOAD & BLOCKA & FOUR)

CONTROL(18)*: CE* and OE* for offset and gain MLUs(8-11).
	(LOAD & !((LOAD & (BLOCK2&!(A12|A13|A14|A15))) |
	(!WRITE & BLOCK2))) | (LOAD & BLOCKA & EIGHT)

CONTROL(19)*: WE* for all offset and gain MLUs.
	!(LOAD & WRITE)

CONTROL(20): Alignment FIFO SI.	

CONTROL(21): Alignment FIFO SO.	

CONTROL(22)*: OE* for the Alignment FIFOs.
	LOAD & !(LOAD & (BLOCK3|BLOCK4|BLOCK5) & (!A13|A14|A15))

CONTROL(23)*: CE* and OE* for the tracking and threshold MLUs(0-3).
	(LOAD & !((LOAD & (BLOCK3&!(A13|A14|A15))) |
        (!WRITE & BLOCK3))) | (LOAD & BLOCKB & ZERO)

CONTROL(24)*: CE* and OE* for the tracking and threshold MLUs(4-7).
	(LOAD & !((LOAD & (BLOCK4&!(A13|A14|A15))) |
        (!WRITE & BLOCK4))) | (LOAD & BLOCKB & FOUR)

CONTROL(25)*: CE* and OE* for the tracking and threshold MLUs(8-11).
	(LOAD & !((LOAD & (BLOCK5&!(A13|A14|A15))) |
        (!WRITE & BLOCK5))) | (LOAD & BLOCKB & EIGHT)

CONTROL(26)*: WE* for all tracking and threshold MLUs.
	!(LOAD & WRITE)

CONTROL(27): SI for the L1 FIFOs.

CONTROL(28): SO for the L1 FIFOs.

CONTROL(29)*: MR* for all FIFOs.
	!(RESET | TM_RESET)

CONTROL(30)*: GW* for the L2 buffers, writes into the L2 buffer.

CONTROL(31): The buffer address of the L1 accepted event(LSB).
	(L1_SRC & L1A0) | (!L1_SRC & L1_ADR(LSB))

CONTROL(32): The buffer address of the L1 accepted event(MSB).
	(L1_SRC & L1A1) | (!L1_SRC & L1_ADR(MSB))

CONTROL(33)*: Enable for the buffers to read out the L2 buffers(0-3).
	!(!WRITE&BLOCK8&!(A6|A7|A8|A9|A10|A11|A12|A13|A14|A15)&!(A2|A3))

CONTROL(34)*: Enable for the buffers to read out the L2 buffers(4-7).
	!(!WRITE&BLOCK8&!(A6|A7|A8|A9|A10|A11|A12|A13|A14|A15)&!(!A2|A3))

CONTROL(35)*: Enable for the buffers to read out the L2 buffers(8-11).
	!(!WRITE&BLOCK8&!(A6|A7|A8|A9|A10|A11|A12|A13|A14|A15)&!(A2|!A3))

CONTROL(36)*: OE* for VME Tower Latches.
	TOWIN_SRC & !(LOAD & (BLOCK0|BLOCK1|BLOCK2) & !(A12|A13|A14|A15))
                                               
CONTROL(37): LE for VME Tower Latch on tower 0.
	BLOCK0 & !A15 & (!(A12|A13|A14)|(!(!A12|A13|A14)&!DS*))
	
CONTROL(38): LE for VME Tower Latch on tower 1.
	BLOCK0 & !A15 & (!(A12|A13|A14)|(!(A12|!A13|A14)&!DS*))
	
CONTROL(39): LE for VME Tower Latch on tower 2.
	BLOCK0 & !A15 & (!(A12|A13|A14)|(!(!A12|!A13|A14)&!DS*))
	
CONTROL(40): LE for VME Tower Latch on tower 3.
	BLOCK0 & !A15 & (!(A12|A13|A14)|(!(A12|A13|!A14)&!DS*))
	
CONTROL(41): LE for VME Tower Latch on tower 4.
	BLOCK1 & !A15 & (!(A12|A13|A14)|(!(!A12|A13|A14)&!DS*))
	
CONTROL(42): LE for VME Tower Latch on tower 5.
	BLOCK1 & !A15 & (!(A12|A13|A14)|(!(A12|!A13|A14)&!DS*))
	
CONTROL(43): LE for VME Tower Latch on tower 6.
	BLOCK1 & !A15 & (!(A12|A13|A14)|(!(!A12|!A13|A14)&!DS*))
	
CONTROL(44): LE for VME Tower Latch on tower 7.
	BLOCK1 & !A15 & (!(A12|A13|A14)|(!(A12|A13|!A14)&!DS*))
	
CONTROL(45): LE for VME Tower Latch on tower 8.
	BLOCK2 & !A15 & (!(A12|A13|A14)|(!(!A12|A13|A14)&!DS*))
	
CONTROL(46): LE for VME Tower Latch on tower 9.
	BLOCK2 & !A15 & (!(A12|A13|A14)|(!(A12|!A13|A14)&!DS*))
	
CONTROL(47): LE for VME Tower Latch on tower 10.
	BLOCK2 & !A15 & (!(A12|A13|A14)|(!(!A12|!A13|A14)&!DS*))
	
CONTROL(48): LE for VME Tower Latch on tower 11.
	BLOCK2 & !A15 & (!(A12|A13|A14)|(!(A12|A13|!A14)&!DS*))
	
CONTROL(49)*: OE* for VME to access the inputs of the alignment FIFOs and
		the data paths for the offset and gain MLUs(0-3).
	!(LOAD & ((BLOCK0&!(A12|A13|A14|A15)) | (BLOCKA&ZERO))) &
	!(!WRITE & BLOCK0 & !(A12|A13|A14|A15))

CONTROL(50)*: OE* for VME to access the inputs of the alignment FIFOs and
		the data paths for the offset and gain MLUs(4-7).
	!(LOAD & ((BLOCK1&!(A12|A13|A14|A15)) | (BLOCKA&FOUR))) &
	!(!WRITE & BLOCK1 & !(A12|A13|A14|A15))

CONTROL(51)*: OE* for VME to access the inputs of the alignment FIFOs and
		the data paths for the offset and gain MLUs(8-11).
	!(LOAD & ((BLOCK2&!(A12|A13|A14|A15)) | (BLOCKA&EIGHT))) &
	!(!WRITE & BLOCK2&!(A12|A13|A14|A15))

CONTROL(52)*: Enables address buffers for the tracking and threshold MLUs(0-3).
	!(LOAD & (BLOCK3&!(A13|A14|A15)) & !BLOCK6)

CONTROL(53)*: Enables address buffers for the tracking and threshold MLUs(4-7).
	!(LOAD & BLOCK4 & !(A13|A14|A15)) & (!BLOCK6|!BLOCK7))

CONTROL(54)*: Enables address buffers for the tracking and threshold MLUs(8-11).
	!(LOAD & (BLOCK5&!(A13|A14|A15)) & !BLOCK7)

CONTROL(55)*: OE* for the data buffers CSUM Access(0-3).
	!(LOAD & ((BLOCK3 & !(A13|A14|A15)) | (BLOCKB&ZERO&WRITE))) & 
	!(!WRITE & (BLOCK3 & !(A13|A14|A15)))

CONTROL(56)*: OE* for the data buffers CSUM Access(4-7).
	!(LOAD & ((BLOCK4 & !(A13|A14|A15)) | (BLOCKB&FOUR&WRITE))) & 
	!(!WRITE & (BLOCK4 & !(A13|A14|A15)))

CONTROL(57)*: OE* for the data buffers CSUM Access(8-11).
	!(LOAD & ((BLOCK5 & !(A13|A14|A15)) | (BLOCKB&EIGHT&WRITE))) & 
	!(!WRITE & (BLOCK5 & !(A13|A14|A15)))

CONTROL(58)*: OE* for the Card Sum chip.
	CSUM_EN

CONTROL(59): CLK for the input latch in Card Sum.

CONTROL(60): CLK for the output latch in Card Sum.

CONTROL(61)*: Enable for the VME data buffers on Card Sum.
	!(!WRITE & BLOCKC & ZERO)

CONTROL(62): CLK for the input latch of ETSUM.

CONTROL(63): CLK for the output latch of ETSUM.

CONTROL(64): Et Threshold(LSB).
	ET_THRESH(LSB)[4]

CONTROL(65): Et Threshold(MSB).
	ET_THRESH(MSB)[5]

CONTROL(66)*: OE* for ETSUM.
	ETSUM_EN

CONTROL(67)*: Enables data buffers on ETSUM.
	!(!WRITE & BLOCKC & FOUR)
	
